Electronic products such as mobile phones, computers, and various consumer products require higher semiconductor functionality and performance in a limited footprint and minimal thickness and weight at the lowest cost. This has driven the industry to increase integration on the individual semiconductor chips.
Conventional chip packing technologies have two inherent limitations: (1) the input/output emerges from only one side of the package (i.e., either from the top or bottom side of the package), and hence integration in both directions along the “z-axis” is difficult, and (2) the footprint of the package is either equal to the die size for fan-in configurations (e.g., WLCSP) or significantly greater than the die size for fan-out configurations.
A recent technique for integrating along the z-axis involves encapsulating a die on a substrate, drilling holes through the encapsulating layer around the periphery of the die, filling the holes with a metal to form vertical connections extending from the PC board, and forming a circuitry layer over the encapsulating layer to permit mounting of a component over the die. This technique suffers from at least the following disadvantages. First, using conventional laser drilling or other known techniques for forming the holes in the encapsulating layer, the pitch between vertical connections is limited to about 125 microns. Second, the drilling process typically results in height variations among the vertical connections, which can produce traces of the circuitry layer that are noncoplanar. Because of this irregularity, a component mounted on top of the circuitry layer may fail to establish sufficient physical and electrical contact with the traces, resulting in a nonfunctioning package. Third, the traces in the circuitry layer typically are flared or enlarged to capture the upper ends of the vertical connections, thereby decreasing the density of the traces. Fourth, the holes in the encapsulating layer must be plated several times in order to form solid vertical interconnections.
Accordingly, there remains room for improvement within the field of semiconductor packaging.